This invention relates generally to semiconductor devices and more particularly dual work function complementary metal oxide semiconductor (CMOS) semiconductor devices.
As is known in the art, it is sometimes desirable to provide CMOS devices in an integrated circuit. A CMOS device includes a pair of electrically isolated field effects transistors (FETs), each transistor having source, drain, and gate electrodes. The source and drain are formed in a semiconductor and are separated by a channel region in the semiconductor. The gates are typically doped silicon (e.g., doped polycrystalline or amorphous silicon) and are disposed over the channels to control the flow of carriers in the channel between the source and drains. One of the transistors has N conductivity type source and drains and is referred to as an NFET, and the other transistor has P conductivity type source and drains as is referred to as a PFET. In a single work function CMOS device, the gates of both transistors are doped with the same conductivity type dopant. In a dual work function CMOS device, both FETs have their gate dopants selected to optimize the performance of the CMOS device. Thus, with a dual work function CMOS device, one of the gates may be doped with a dopant different from the dopant of the other one of the gates.
In accordance with one embodiment of the invention, a method is provided for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is lithographically patterned comprising selectively removing a portion of such first doped layer to expose a first portion of the gate oxide with the first doped layer remaining disposed over a second laterally disposed portion of the gate oxide. A second doped layer is deposited over the patterned first doped layer. The second doped layer has a dopant different from, for example, a conductivity type opposite to, the dopant of the first doped layer. A portion of the second doped layer is deposited over the exposed first portion of the gate oxide and over the portion of the first doped layer to provide a pair of vertically positioned regions. A lower region comprises a portion of the first doped layer and an upper region comprising a portion of the second doped layer. The second doped layer is lithographically patterned to form a pair of laterally spaced gates for the transistors, one of such gates comprising the patterned first doped layer and the other one of the gates comprising the patterned pair of vertically positioned regions.
In accordance with another embodiment, the second dopant is distributed in the second gate among a lower portion of the first dopant in such second gate.
In accordance with another embodiment, the distribution comprises heating the dopant in the second gate.
In accordance with another embodiment, the first doped layer depositing comprises forming the first doped layer with silicon.
In accordance with another embodiment, the first and second doped layer depositing comprises forming the first and second doped layer with silicon.
In accordance with another embodiment, the silicon is doped polycrystalline or doped amorphous silicon.
In accordance with another embodiment, the first and second doped layers are deposited to different thickness.
In accordance with another feature of the invention, a pair of field effect transistors is provided. Such pair of transistors includes a semiconductor substrate. A gate oxide is disposed over a surface of the substrate. A first gate for a first one of the transistors is disposed over a first portion of the gate oxide, such first gate comprising a first dopant region. A second gate for a second one of the transistors is disposed over a second portion of the gate oxide, such second portion of the gate oxide being laterally spaced from the first portion of the gate oxide. The second gate comprises a pair of vertically disposed doped regions. The second one of the doped regions comprises the first dopant and is disposed above the first doped region. In one embodiment, the first dopant has a first conductivity type dopant is opposite to the second conductivity type dopant.
In accordance with one embodiment of the invention, an upper portion of the second conductivity type dopant in the second gate is distributed among a lower portion of the first dopant in such second gate.
In accordance with another embodiment, the first gate comprises doped silicon.
In accordance with still another embodiment, the silicon is polycrystalline or amorphous silicon.
In accordance with another embodiment, the first gate comprises doped silicon and the pair of regions of the second gate comprise silicon.
In accordance with another embodiment, the silicon is polycrystalline or amorphous silicon.
In accordance with another embodiment, an upper portion of the second dopant in the second gate is distributed among a lower portion of the first dopant in such second gate.